1. Field of the Invention
This invention relates generally to a process for packaging integrated circuits and, more particularly, to a packaging process that eliminates lead frame structures and wire bonds, and allows testing while the integrated circuit is still in wafer format.
2. Discussion of the Related Art
As is well understood in the art, many integrated circuit chips are patterned and formed together on an integrated circuit wafer. The wafer may be 3-15 inches in diameter, and include hundreds or thousands of integrated circuit chips symmetrically disposed in a matrix configuration on the wafer depending on the circuit complexity. Once the integrated circuit chips are fabricated, the wafer is cut between the integrated circuit chips to separate the chips from the wafer. The chips are then tested for performance.
Once the integrated circuit chip is separated from the wafer, it is sometimes packaged in a packaging assembly that provides environmental protection and the like. Generally, the integrated circuit chip is mounted to a metallized ground plane to provide a ground reference and thermal coupling to remove heat from the integrated circuit chip. A lead frame is mounted to the assembly to provide power, signal and ground connections to other circuit elements outside of the package. Wire bonds are used to provide electrical connections between the lead frame and the chip, and between the lead frame and the ground plane. However, the wire bonds cause parasitic inductances and capacitances that compromise performance of the integrated circuit, especially at high frequencies.
FIG. 1 is a cross-sectional view of a packaging assembly 10 for packaging an integrated circuit chip 12 of the type discussed above. The integrated circuit chip 12 is mounted to a back-side ground plane 14 by a thermally and electrically conductive attachment layer 16, such as solder. The ground plane 14 is mounted to a die paddle 18 associated with a lead frame 20. The lead frame 20 includes a plurality of separate leads 24 that are electrically isolated from each other and from the die paddle 18. The leads 24 provide signal and power connections to the integrated circuit chip 12 from other circuit elements and systems. Metal traces 26 are deposited on top of the leads 24 within the packaging assembly 10 to provide a good electrical contact thereto. Signal wire bonds 28 are electrically connected to the traces 26 and to the chip 12 to make electrical connections thereto. Additionally, ground wire bonds 30 are electrically coupled to the ground plane 14 and the traces 26, or the ground plane 14 and the chip 12, as shown. A flowable solder layer 32 is deposited on the bottom surface of the leads 24 and the die paddle 18 to provide good electrical, mechanical and thermal coupling.
A moldable material, such as a plastic compound, is injection molded around the integrated circuit chip 12, the wire bonds 28 and 30 and the lead frame 20 to seal the components and provide a protective cover 36. The packaging assembly 10 is surface mounted to a circuit board (not shown) including other packaging assemblies to form an electrical system. The solder layer 32 is heated so that solder flows up the sides of the leads 24 to make good electrical connection to the circuit board.
The leads 24 of the lead frame 20 of the packaging assembly 10 shown in FIG. 1 extend beyond the sides of the protective cover 36. Thus, the size of the assembly 10 is larger than it needs to be. FIG. 2 is a cross-sectional view of another known packaging assembly 40 that is a variation of the packaging assembly 10 where like elements are identified by the same reference numeral. In this embodiment, the molding forming the cover 36 has been molded to form straight sides with the leads 24 so that when the solder flows up the side of the leads 24, it still makes electrical contact thereto.
In accordance with the teachings of the present invention, a packaging assembly for an integrated circuit is disclosed that eliminates the wire bonds required in the prior art, and provides integrated circuit packaging while the circuit is still in a wafer format. The wafer substrate on which the many integrated circuits have been fabricated is patterned and etched to form signal and power vias through the substrate around an outside periphery of each circuit, and to form ground vias through the substrate beneath the circuits. The combination of a portion of the wafer substrate, the vias and the integrated circuit define an integrated circuit die. Bonding pads are deposited on a top surface and a bottom surface of the wafer substrate that are electrically coupled to the signal vias. A back-side ground plane is provided in electrical contact with the ground vias.
A top protective layer is deposited over all of the integrated circuits, and a photoresist is deposited, patterned and etched on the bottom surface of the wafer substrate so that wafer substrate material can be removed between the dies. A bottom protective layer is then deposited on a bottom surface of the wafer substrate so that it fills the areas between the dies where the substrate material has been removed. The bottom protective layer is then patterned and etched to provide electrical vias therethrough in contact with the back-side metal layer and the signal pads to make electrical contact thereto outside of the packaging assembly. The wafer is then diced along edges of the dies so that the various vias on the sides of the dies are exposed to provide electrical signals to the circuit within the assembly.
Additional advantages and features of the present invention will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings.